[2019] Design tradeoffs in multimodal CMOS-MEA systems

The patch clamp has been considered the golden standard to access the cell’s intracellular environment, enabling accurate measurement of action potentials (APs) in in-vitro cell cultures. The significant invasiveness and low analytical throughput of the patch clamping technique has led to the development of microelectrode array (MEA) structures, integrated on the bottom of cell culture chambers. Current MEA devices, however, are limited both in spatial resolution (>10µm) and in number of integrated electrodes (<100) due to the need for external wiring and readout circuitry. The adoption of complementary metal-oxide semiconductor (CMOS) technology has enabled the integration of high-density MEA systems (>103 sites) with recording and stimulating circuits into a monolithic chip solution. Integration of high-density MEAs and multi-modal readout electronics, however, is subject to significant design tradeoffs, including pixel size, ratio, power consumption, area, frame rate, resolution etc. This project will be focused on identifying and exploring these tradeoffs and on the design of an optimised CMOS-MEA chip for heart-on-a-chip applications.

The project will consists of 3 main activities: - Define a design space for CMOS-MEA systems - Model and optimize the design of integrated MEAs for specific applications - Design the switch matrix, decoders and analog front-end in Cadence using a 0.18µm CMOS process.

Assignment

- System level design in Matlab/Simulink - Modeling and optimization of MEA design - Schematic and layout design comparison of CMOS-MEA architectures

Requirements

- Analog CMOS design I & II - Analog Integrated Circuit Design

Contact

dr. Virgilio Valente

Bioelectronics Group

Department of Microelectronics

Last modified: 2019-12-20