MSc thesis project proposal

[2018] Background Calibration and Adaptive Tuning Methods for Time-Mode Subtraction Based Time-to-Digital Converters

With the scaling of the technology nodes, while the performance of the digital systems improves, the supply voltage, and thus the headroom available for analog signal processing, scales down as well. This imposes a strict limit on the analog signal processing capabilities. One solution to this problem is using time-mode signal processing (TMSP) techniques [1]–[3]. One of the most important blocks in such a system is the time-to-digital converter (TDC), which enables such a system to communicate with a digital environment.

A TDC resolves a time difference into a digital value. The time difference can either be the difference between two separate signals, usually the start and the stop signals, or the time between the edges of a single signal. The result of the conversion is a digital word rep- resenting the time difference value, similar to the digital output word in analog-to-digital (AD) conversion. In addition to TDSP systems, TDCs find many applications in scientific experiments, such as digital phase-locked-loop (DPLL) applications, and on-chip time measurement and testing.

In this project, we aim to develop background calibration and biosignal specific (EEG, ECG, ECOG, etc.) adaptive tuning methods for a recently developed asynchronous TDC which utilizes a time-based subtraction method. The developed TDC will be a part of a neural recording chip that utilizes time-mode signal processing. Due to the developed TDC’s similarities to Successive Approximation and Pipelined Analog-to-Digital converters (ADC), calibration methods used for these ADCs may be adopted to enhance the performance of the TDC.

[1] F. Yuan, “Cmos time-to-digital converters for mixed-mode signal pro- cessing,” The Journal of Engineering, January 2014. [Online]. Available: http://digital-library.theiet.org/content/journals/10.1049/joe.2014.0044

[2] D. Miyashita, R. Yamaki, K. Hashiyoshi, H. Kobayashi, S. Kousai, Y. Oowaki, and Y. Unekawa, “An LDPC decoder with time-domain analog and digital mixed-signal processing,” IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 73–83, Jan 2014.

[3] Z. Chen and J. Gu, “Analysis and design of energy efficient time domain signal processing,” in Proceedings of the 2016 International Symposium on Low Power Electronics and Design. ACM, 2016, pp. 100–105.

Assignment

The exact timeline of the project will be determined in close collaboration with the student. The project will consist of study and implementation of the calibration and tuning methods both at the algorithmic and hardware level. Study of both the properties of biosignals as well as the implementation specifics of the developed TDC will take place. Based on the studies and simulations, calibration and tuning methods will first be implemented in higher level modeling languages (Mathematica or Matlab, then Verilog-AMS), then based on the developed models, a synthesizable Verilog model together with the required analog circuitry will be developed and then a hardware implementation will be realized. Expected hardware outcome of the project is a background calibration and signal specific tuning engine that is implemented in a standard CMOS technology, whose feature size will be chosen during the course of the project.

Requirements

For this project, we are looking for a student with a strong mathematical background and with previous experience with both mixed-signal design and digital design flow. Experience with biosignals and a scripting language such as Python is a plus.

Contact

dr. Can Akgun

Bioelectronics Group

Department of Microelectronics

Last modified: 2018-03-14