MSc thesis project proposal
High Speed Adaptive Equalization for Gigabit Ethernet Receiver Design
Gigabit Ethernet for automotive employs a high baud rate (750MHz) for communicating over an unshielded twisted pair using PAM (pulse amplitude modulation). The receiver has to learn the channel impulse response (CIR) of the wire from the incoming data stream as wires differ in length per connection. The receiver must also track (CIR) during normal operation due to drastic temperature variations in the car. Therefore Decision-Feedback-Equalizer (DFE) based adaptive filters are the typical choice for the equalization step. The challenge is to investigate a low complexity adaptive DFE algorithm for a high speed equalizer targeting a baud rate of 750MHz. Moreover, due to the increased length of the CIR, frequency domain processing can also be an attractive option for reducing implementation complexity. This project will be a joint effort between NXP in Eindhoven (contact person Dr. Ozgun Paker, firstname.lastname@example.org) and the Circuits and Systems group of the Delft University of Technology.
Project outside the universityNXP, Eindhoven
AssignmentMilestones: i) Implement conventional hard-decision time-domain DFE-based equalization in matlab as a reference design; ii) Investigate possible algorithmic options below and benchmark the algorithmic performance in matlab vs. the reference design: frequency domain adaptive DFE equalization, soft-decision based DFE equalization, frequency-domain and soft-decision based DFE equalization, or another promising option proposed by the student; iii) Compare all these options with respect to implementation complexity.
RequirementsFor this project, we are looking for a master student in either electrical engineering, applied physics, mathematics, computational science or any related study. Programming skills in Matlab and/or C/C++ and basic knowledge of signal processing and digital communications are highly appreciated. Good spoken and written English is a must. Expected project duration is about 9 months.
prof.dr.ir. Geert Leus
Circuits and Systems Group
Department of Microelectronics
Last modified: 2015-10-30