AER for multi FPGA Neuromorphic Systems

In a complex hierarchical multi-FPGA AER systems it is crucial to have available proper computer interfaces for (a) reading AER traffic and (b) for injecting synthesized or recorded AER traffic into AER buses. We need to optimize the throughput of the AER bus, hence we will exploit the properties of neuromorphic data. Also, we have to employ an optimal bus topology (multi-ring) and we do require a routing strategy. All of this needs to be developed on top of high-speed serial interface blocks in a XILINX device (SERDES). Clearly, this interface has to be free of transmit and receive errors......

Assignment

Develop the architecture for the communications system, evaluate, and design. Build a prototype.

Requirements

C Language, VHDL, digital systems, networks

Contact

Last modified: 2023-01-13